CMOS SPAD array for 3D ranging

Many social needs (e.g. Safety and Security) and biomedical applications (e.g. Molecular Imaging and Biological Analysis) require the acquisition of images at low light levels, at video or even higher frame rates and also with distance-resolution. This project aims to conceive, develop and test microelectronic technologies for cost-effective manufacturing of very fast, highly sensitive, multy-spectral 2D and 3D SPAD (Single Photon Avalanche Diode) cameras running at higher speed than standard video-rate.

We fabricated two SPAD arrays (32 x 32 pixels, 30 µm SPAD diameter, and 32 x 16 pixels, 100 µm SPAD diameter) for 3D direct Time-Of-Flight ranging measurements. Each pixel can operate in photon counting (6 bit asynchronous counter) and in photon timing (Time to Digital Converter with 312 ps timing resolution).

Layout and micrograph of the 32 x 32 array for direct Time of Flight

We also fabricated a 64 x 32 SPAD array able to process at the pixel-level intensity-data and depth-ranging information through indirect Time-of-Flight measurement (i.e. distance information is retrieved by measuring the phase shift between the modulated light source and the reflected signal), by using either continuous-wave or pulsed light modulation. The iTOF smart pixel has independently 9-bit selectable counters: one of the three counters integrates the background light, thus storing 2-D intensity information; the two remaining counters, are bidirectional and performs light demodulation, thus enabling 3D mapping of rapidly changing scenes in light starved environments. Row and column access circuitry, consisting of shift registers, allows sequential addressing of data; a column multiplexer scans the bitlines and global electronics handles clock managing, read-out operations and array initialization. The array can operate at high clock frequency (up to 100 MHz) and the read-out is performed both on the upper and the lower end of the pixel array to reduce the minimum frame integration time (31 µs).

Layout and micrograph of the 64 x 32 array for indirect Time of Flight

Finally, since a single standard CMOS wafer with SPAD and electronics placed side-by-side results in a limited fill-factor, we are working on the design of a vertical wafer-bonded flipped-chip back-side illuminated imager, with SPAD and pixel electronics placed one over the other. The goal is to reach a beyond state-of-the-art performances with cost-effective processing technology for back-side illumination based on the combination of SPAD detector wafers processed in a silicon-on-insulator (SOI) technology, flipped and bonded on standard CMOS wafers with the electronics. We designed an array based on 32x32 pixels, that are read-out in parallel.

Layout of one pixel of CMOS electronics

Publications

Contacts

Franco Zappa - franco.zappa@polimi.it
Simone Tisa - simone.tisa@polimi.it